? semiconductor components industries, llc, 2003 january, 2003- rev. 8 1 publication order number: nb100lvep222/d nb100lvep222 2.5v/3.3v 1:15 differential ecl/pecl 1/ 2 clock driver the nb100lvep222 is a low skew 1:15 differential 1/ 2 ecl fanout buffer designed with clock distribution in mind. the lvecl/lvpecl input signal pairs can be used in a differential configuration or single-ended (with v bb output reference bypassed and connected to the unused input of a pair). either of two fully differential clock inputs may be selected. each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1x or 1/2x of the input frequency. the l vep222 specifically guarantees low output to output skew. optimal design, layout, and processing minimize skew within a device and from lot to lot. this device is an improved version of the mc100lve222 with higher speed capability and reduced skew. the fsel pins and clk_sel pin are asynchronous control inputs. any changes may cause indeterminate output states requiring an mr pulse to resynchronize any 1/2x outputs (see figure 3). unused output pairs should be left unterminated (open) to reduce power and switching noise. the nb100lvep222, as with most ecl devices, can be operated from a positive v cc supply in lvpecl mode. this allows the lvep222 to be used for high performance clock distribution in +2.5/3.3 v systems. in a pecl environment series or thevenin line, terminations are typically used as they require no additional power supplies. for more information on using pecl, designers should refer to application note an1406/d. for a spice model, refer to application note an1560/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single- ended lvpecl input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. single- ended clk input operation is limited to a v cc 3.0 v in lvpecl mode, or v ee -3.0 v in necl mode. ? 20 ps output-to-output skew ? 85 ps part-to-part skew ? selectable 1x or 1/2x frequency outputs ? lvpecl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = -2.375 v to -3.8 v ? internal input pulldown resistors ? performance upgrade to on semiconductor's mc100lve222 ? v bb output device package shipping ordering information nb100lvep222fa lqfp-52 160 units/tray nb100lvep222far2 lqfp-52 1500/tape & reel *for additional information, see application note and8002/d a = assembly location wl = wafer lot yy = year ww = work week 52-lead lqfp thermally enhanced case 848h fa suffix marking diagram* nb100 lvep222 awlyyww 52 1 http://onsemi.com
nb100lvep222 http://onsemi.com 2 qc2 qc3 qc2 qc0 qc1 v cc0 qd3 40 41 42 43 44 45 46 47 25 24 23 22 21 20 19 12345678 39 38 37 36 35 34 33 32 26 qd3 qd2 qd2 qd1 qd1 qd0 qd0 v cc0 qb0 qb0 qb1 qb1 qb2 qb2 v cc0 all v cc , v cco , and v ee pins must be externally connected to appropriate power supply to guarantee proper operation. the thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit. this exposed pa d is electrically connected to v ee internally. figure 1. 52-lead lqfp pinout (top view) fsela fselb clk_sel clk1 nb100lvep222 clk0 v bb fselc fseld v ee 910111213 48 49 50 51 52 31 30 29 28 27 18 17 16 15 14 qd5 qd5 qd4 qd4 v cc0 qa0 qa0 qa1 qa1 v cc0 v cc mr clk0 clk1 qc0 qc1 nc nc v cc0 qc3 v cc0 pin description function ecl differential input clock ecl differential input clock ecl clock select ecl master reset ecl differential outputs ecl differential outputs ecl differential outputs ecl differential outputs ecl 1 or 2 select reference voltage output positive supply negative supply no connect pin clk0*, clk0 ** clk1*, clk1 ** clk_sel* mr* qa0:1, qa0:1 qb0:2, qb0:2 qc0:3, qc0:3 qd0:5, qd0:5 fseln* v bb v cc , v cco v ee *** nc * pins will default low when left open. ** pins will default high when left open. *** the thermally conductive exposed pad on the bottom of the package is electrically connected to v ee internally. function table input function active clk0 1 mr clk_sel fseln lh reset clk1 2
nb100lvep222 http://onsemi.com 3 clk0 clk0 clk1 clk1 clk_sel qa0:1 mr 2 2 1 qa0:1 qb0:2 3 qb0:2 v bb fselb qc0:3 4 qc0:3 fselc qd0:5 6 qd0:5 fseld figure 2. logic diagram fsela v cc v ee figure 3. master reset (mr) timing diagram clk mr q ( 2) q ( 1)
nb100lvep222 http://onsemi.com 4 attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity (note 1) level 3 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 transistor count 821 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v -6 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i ? ?? ? ? v ee 6 to 0 -6 to 0 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (see application information) 0 lfpm 500 lfpm 52 lqfp 52 lqfp 35.6 30 c/w c/w jc thermal resistance (junction-to-case) (see application information) 0 lfpm 500 lfpm 52 lqfp 52 lqfp 3.2 6.4 c/w c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. lvpecl dc characteristics v cc = 2.5 v; v ee = 0 v (note 3) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 125 150 104 130 156 112 140 168 ma v oh output high voltage (note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 4) 555 680 900 555 680 900 555 680 900 mv v ih input high voltage (single-ended) (note 5) 1335 1620 1335 1620 1275 1620 mv v il input low voltage (single-ended) (note 5) 555 900 555 900 555 900 mv v ihcmr input high voltage common mode range (differential configuration) (note 6) (figure 5) 1.2 2.5 1.2 2.5 1.2 2.5 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 3. input and output parameters vary 1:1 with v cc . v ee can vary + 0.125 v to -1.3 v. 4. all loading with 50 to v cc - 2.0 v. 5. do not use v bb pin #10 at v cc < 3.0 v (see and8066). 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep222 http://onsemi.com 5 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 7) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 125 150 104 130 156 112 140 168 ma v oh output high voltage (note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 8) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mv v ih input high voltage (single-ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single-ended) 1355 1700 1355 1700 1355 1700 mv v bb output reference voltage (note 9) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) (figure 5) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 7. input and output parameters vary 1:1 with v cc . v ee can vary + 0.925 v to -0.5 v. 8. all loading with 50 to v cc -2.0 v. 9. single ended input operation is limited v cc 3.0 v in lvpecl mode. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. lvnecl dc characteristics v cc = 0.0 v; v ee = -3.8 v to -2.375 v (note 11) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 125 150 104 130 156 112 140 168 ma v oh output high voltage (note 12) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mv v ol output low voltage (note 12) -1945 -1820 -1600 -1945 -1820 -1600 -1945 -1820 -1600 mv v ih input high voltage (single ended) -1 165 -880 -1 165 -880 -1 165 -880 mv v il input low voltage (single ended) -1945 -1600 -1945 -1600 -1945 -1600 mv v bb output reference voltage (note 13) -1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 14) (figure 5) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 11. input and output parameters vary 1:1 with v cc . 12. all loading with 50 to v cc - 2.0 v. 13. single ended input operation is limited v ee -3.0v in necl mode. 14. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep222 http://onsemi.com 6 ac characteristics v cc = 2.375 to 3.8 v; v ee = 0.0 v or v cc = 0.0 v; v ee = -2.375 to -3.8 v (note 15) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v opp differential output voltage (figure 4) f out = 50 mhz f out = 0.8 ghz f out = 1.0 ghz 500 550 500 600 650 650 500 525 425 600 650 650 500 500 400 600 650 600 mv t plh t phl propagation delay (differential configuration) clkx-q x mr-q xx 650 700 800 900 900 1200 700 700 875 900 1000 1200 850 700 975 900 1150 1200 ps t skew within-device skew (note 16) ( 1 mode) - qa[0:1] - qb[0:2] - qc[0:3] - qd[0:5] - qa n , qb n , qd n - all outputs 10 10 20 10 10 20 40 40 60 40 40 60 10 10 20 10 10 20 40 40 60 40 40 60 10 10 20 10 10 20 40 40 60 40 40 60 ps t skew within-device skew (note 16) ( 2 mode) - qa[0:1] - qb[0:2] - qc[0:3] - qd[0:5] - qa n , qb n , qd n - all outputs 15 15 20 15 15 20 70 70 70 70 70 70 10 10 20 10 10 20 40 40 50 40 40 50 15 10 15 15 15 15 70 40 70 70 70 70 ps t skew device-to-device skew (differential configuration) (note 17) 85 300 85 300 85 300 ps t jitter random clock jitter (figure 4) (rms) 1 5 1 4 1 5 ps v pp input swing (differential configuration) (note 18) (figure 5) 150 800 1200 150 800 1200 150 800 1200 mv dco output duty cycle 49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 % t r /t f output rise/fall time 20%-80% 100 200 300 100 200 300 150 250 350 ps 15. measured with lvpecl 750 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc - 2 v. 16. skew is measured between outputs under identical transitions and operating conditions. 17. device-to-device skew for identical transitions at identical v cc levels. 18. v pp is the differential configuration input voltage swing required to maintain ac characteristics including t pd and device-to-device skew. figure 4. output voltage (v opp ) versus input frequency and random clock jitter (t jitter ) @ 25 c input frequency (ghz) 0.1 1.5 900 800 700 600 500 400 300 200 v opp , output voltage (mv) 9.0 8.0 7.0 6.0 10 5.0 4.0 3.0 2.0 1.0 0 rms jitter (ps) 1.0 2.0 q amp ( 2) q amp ( 1) rms jitter 0.5
nb100lvep222 http://onsemi.com 7 receiver device driver device q q d d 50 50 v tt v tt = v cc - 2.0 v figure 5. lvpecl differential input levels v ih (diff) v il (diff) v ee v cc (lvpecl) v ihcmr v pp figure 6. typical termination for output driver and device evaluation (refer to application note and8020 - termination of ecl logic devices) resource reference of application notes an1405 - ecl clock distribution techniques and8002 - marking and date codes and8009 - eclinps plus spice i/o model kit and8020 - termination of ecl logic devices and8066 - interfacing with eclinps for an updated list of application notes, please see our website at http://onsemi.com.
nb100lvep222 http://onsemi.com 8 applications information using the thermally enhanced package of the nb100lvep222 the nb100lvep222 uses a thermally enhanced 52-lead lqfp package. the package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. this exposed metal pad will provide the low thermal impedance that supports the power consumption of the nb100lvep222 high-speed bipolar integrated circuit and will ease the power management task for the system design. in multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the nb100lvep222. the size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. however, the solderable area should be at least the same size and shape as the exposed pad on the package. direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. the thermal vias will connect the exposed pad of the package to internal copper planes of the board. the number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. the recommended thermal land design for nb100lvep222 applications on multi-layer boards comprises a 4 x 4 thermal via array using a 1.2 mm pitch as shown in figure 7 providing an efficient heat removal path. figure 7. recommended thermal land pattern all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 the via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. solder wicking inside the via may result in voiding during the solder process and must be avoided. if the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. this will supply enough solder paste to fill those vias and not starve the solder joints. the attachment process for the exposed pad package is equivalent to standard surface mount packages. figure 8, recommended solder mask openingso, shows a recommended solder mask opening with respect to a 4 x 4 thermal via array. because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in figure 8. for the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. figure 8. recommended solder mask openings all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 0.2 1.0 1.0 0.2 proper thermal management is critical for reliable system operation. this is especially true for high-fanout and high output drive capability products. for thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: table 1. thermal resistance * lfpm ja c/w jc c/w 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * junction to ambient and junction to board, four-conductor layer test board (2s2p) per jesd 51-8 these recommendations are to be used as a guideline, only. it is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. the exposed pad of the nb100lvep222 package is electrically shorted to the substrate of the integrated circuit and v ee . the thermal land should be electrically connected to v ee .
nb100lvep222 http://onsemi.com 9 package dimensions lqfp 52 lead exposed pad package case 848h-01 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: mm. 3. datum plane e" is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting plane. 4. datum x", y" and z" to be determined at datum plane datum e". 5. dimensions m and l to be determined at seating plane datum t". 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum pland e". 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum d dimension by more than 0.08 (0.003). dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). dim a min max min max inches 10.00 bsc 0.394 bsc millimeters b 10.00 bsc 0.394 bsc c 1.30 1.50 0.051 0.059 d 0.22 0.40 0.009 0.016 f 0.45 0.75 0.018 0.030 g 0.65 bsc 0.026 bsc h 1.00 ref 0.039 bsc j 0.09 0.20 0.004 0.008 k 0.05 0.20 0.002 0.008 l 12.00 bsc 0.472 bsc m 12.00 bsc 0.472 bsc n 0.20 ref 0.008 ref p 0 7 0 7 r 0 --- 0 --- s --- 1.70 --- 0.067 v 12 ref 12 ref w 12 ref 12 ref aa 0.20 0.35 0.008 0.014 ab 0.07 0.16 0.003 0.006 ac 0.08 0.20 0.003 0.008 ad 4.58 4.78 0.180 0.188 ae 4.58 4.78 0.180 0.188 -y- 0.05 (0.002) s 1 b b/2 13 14 26 27 39 40 52 -x- l l/2 -z- m m/2 a a/2 aj aj z 0.20 (0.008) t x-y 4 pl z 0.20 (0.008) e x-y -t- seating plane g ag ag d 52 pl z 0.08 (0.003) m t x-y -e- 0.10 (0.004) t 1 13 14 26 27 39 40 52 exposed pad view ag-ag ad ae detail ah detail ah ???? ???? aa d ab j detail aj-aj ref base metal plating z 0.08 (0.003) m y t-u s c k v r w n f h p ac 0.25 gage plane 48 pl
nb100lvep222 http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nb100lvep222/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
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